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74VHC125 Quad Buffer with 3-STATE Outputs
August 1993 Revised March 1999
74VHC125 Quad Buffer with 3-STATE Outputs
General Description
The VHC125 contains four independent non-inverting buffers with 3-STATE outputs. It is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology and achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.
Features
s High Speed: tPD = 3.8 ns (typ) at VCC = 5V s Lower power dissipation: ICC = 4 A (max) at TA = 25C s High noise immunity: VNIH = VNIL = 28% VCC (min) s Power down protection is provided on all inputs s Low noise: VOLP = 0.8V (max)
Ordering Code:
Order Number 74VHC125M 74VHC125SJ 74VHC125MTC 74VHC125N Package Number M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names An, Bn On Description Inputs Outputs
Function Table
Inputs An L L H
H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance X = Immaterial
Output Bn L H X On L H Z
(c) 1999 Fairchild Semiconductor Corporation
DS011632.prf
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74VHC125
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT ) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260C -0.5V to +7.0V -0.5V to +7.0V -0.5V to VCC + 0.5V -20 mA 20 mA 25 mA 50 mA -65C to +150C
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC = 3.3V 0.3V VCC = 5.0V 0.5V 0 100 ns/V 0 20 ns/V 2.0V to +5.5V 0V to +5.5V 0V to VCC -40C to +85C
Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0 - 5.5 2.0 3.0 - 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IOZ IIN ICC 3-STATE Output Off-State Current Input Leakage Current Quiescent Supply Current 5.5 4.0 40.0 A VIN = VCC or GND 0 - 5.5 0.1 1.0 A 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.25 2.0 3.0 4.5 TA = 25C Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 2.5 V A IOL = 4 mA IOL = 8 mA VIN = VIH or VIL VOUT = VCC or GND VIN = 5.5V or GND V V IOH = -4 mA IOH = -8 mA VIN = VIH IOL = 50 A or VIL V Typ Max TA = -40C to +85C Min 1.50 0.7 VCC 0.50 0.3 VCC Max Units V V VIN = VIH IOH = -50 A or VIL Conditions
Noise Characteristics
Symbol VOLP (Note 3) VOLV (Note 3) VIHD (Note 3) VILD (Note 3) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum HIGH Level Dynamic Input Voltage 5.0 1.5 V CL = 50 pF 5.0 3.5 V CL = 50 pF 5.0 -0.5 -0.8 V CL = 50 pF VCC (V) 5.0 TA = 25C Typ 0.5 Limits 0.8 V CL = 50 pF Units Conditions
Note 3: Parameter guaranteed by design.
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74VHC125
AC Electrical Characteristics
Symbol tPLH tPHL Parameter Propagation Delay Time 5.0 0.5 tPZL tPZH 3-STATE Output Enable Time 5.0 0.5 tPLZ tPHZ tOSLH tOSHL CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance
Note 4: Parameter guaranteed by design. tOSLH = |tPLHmax - t PLHmin|; tOSHL = |tPHLmax - tPHLmin|. Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (OPR.) = CPD * VCC * fIN + ICC/4 (per bit).
VCC (V) 3.3 0.3
TA = 25C Min Typ 5.6 8.1 3.8 5.3 5.4 7.9 3.6 5.1 9.5 6.1 Max 8.0 11.5 5.5 7.5 8.0 11.5 5.1 7.1 13.2 8.8 1.5 1.0 4 6 14 10
TA = -40C to +85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 9.5 13.0 6.5 8.5 9.5 13.0 6.0 8.0 15.0 10.0 1.5 1.0 10
Units ns ns ns ns ns ns pF pF pF
Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF RL = 1 k CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF RL = 1 k CL = 50 pF CL = 50 pF (Note 4) CL = 50 pF CL = 50 pF VCC = Open VCC = 5.0V (Note 5)
3.3 0.3
3-STATE Output Disable Time Output to Output Skew
3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5
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74VHC125
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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74VHC125
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
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74VHC125 Quad Buffer with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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